A Sub-1V, 1.6mW, 2.06GHz clock generator for mobile SoC applications in 32nm CMOS

A fully integrated Phase-Locked Loop (PLL) as a clock generator is described in an advanced 32nm CMOS technology. Features include adaptive bandwidth architecture, automatic frequency calibrator (AFC), a sub-1V V/I converter operation, feedback control to minimize charge-pump current mismatch, and a fully integrated loop filter. The whole PLL measures power consumption of 1.6mW when VCO oscillates at 2.06GHz under the supply voltage of 0.8V. The total die size is 300μm by 300μm, including global power/ground routing, input ESD cells and on-chip power decoupling capacitors. The PLL has a glitch-free post divider to prevent any glitches during the output frequency switching. The circuit has been proven to operate from a 0.8V supply and consumes 1.6mW with the less than 4ps rms jitter over production test.