A mixed-signal VLSI neural network with on-chip learning

The design and implementation of a mixed-signal neural integrated circuit for general purpose applications is presented. This structure is composed of regular arrays of synaptic multipliers, neurons and registers. A distributed resistive type neuron architecture is used to take advantage of self-scaling property of the neurons. A distributed architecture allows the chip to be used in different network sizes. Training is done on-chip with MADALINE rule III. Although MADALINE rule III is more robust for analog and mixed-signal designs with good overall speed during the training phase, there is not many reported works applying this technique. The problems of node addressing and routing are solved by performing the operations in current mode through a summing node. The simulation results for an XOR problem are presented to show the generality of the design.