Title :
Integrator-chain multiplier
Author :
Ho, Hsu Liang ; Smith, Kenneth C.
Author_Institution :
Dept. of Electr. Eng., Toronto Univ., Ont., Canada
Abstract :
An MVL (multiple-valued-logic) multiplier circuit scheme, called the integrator-chain method, is presented. This circuit scheme is particularly suited to the switched-capacitor topology. The feasibility of circuit implementations of the integrator-chain multiplier design in various number systems, including the sign-bit number representation, the R´s and (R-1)´s complement representations, and the signed-digit-number (SDN) system, is discussed. It is demonstrated by simulation that a 4×4 multiplier circuit operating in a radix-7 SDN system has a size comparable to the simplest binary counterpart
Keywords :
digital arithmetic; many-valued logics; multiplying circuits; 4×4 multiplier circuit; circuit; integrator-chain method; integrator-chain multiplier design; multiple valued logic multiplier circuit; radix-7 SDN system; sign-bit number representation; signed-digit-number; switched-capacitor topology; Adders; Circuit simulation; Circuit topology; Clocks; Decision making; Logic; Signal generators; Signal processing; Switches; Voltage;
Conference_Titel :
Multiple-Valued Logic, 1990., Proceedings of the Twentieth International Symposium on
Conference_Location :
Charlotte, NC
Print_ISBN :
0-8186-2046-3
DOI :
10.1109/ISMVL.1990.122648
