Title :
Experimental via characterization for the signal integrity verification of discontinuous interconnect line
Author :
Kim, Hyewon ; Kim, Dongchul ; Eo, Yungseon
Author_Institution :
Electr. & Comput. Eng., Hanyang Univ., Ansan, South Korea
Abstract :
Interconnect lines with inter-layer vias are experimentally characterized by using high-frequency S-parameter measurements. Test patterns are designed and fabricated using a package process and measured using Vector Network Analyzer (VNA) up to 25 GHz. Then, by modeling a via as a circuit, its model parameters are determined. It is shown that the circuit model has excellent agreement with the measured S-parameters. The circuit performance of the lines with inter-layer vias is evaluated by using the developed circuit model. Thereby, it is shown that via may have a substantially deteriorative effect on the signal integrity of high-speed integrated circuits.
Keywords :
S-parameters; integrated circuit interconnections; integrated circuit modelling; deteriorative effect; discontinuous interconnect line; high-frequency S-parameter measurements; package process; signal integrity verification; test patterns; vector network analyzer; via characterization; Capacitance; Data models; Impedance measurement; Integrated circuit interconnections; Integrated circuit modeling; Scattering parameters; Transmission line measurements; S-parameter; circuit model; eye-diagram; via;
Conference_Titel :
SoC Design Conference (ISOCC), 2010 International
Conference_Location :
Seoul
Print_ISBN :
978-1-4244-8633-5
DOI :
10.1109/SOCDC.2010.5682933