Title :
A systolic approach to multistage interconnection network design
Author :
Chen, Chung-Han ; Bhuyan, Laxmi N.
Author_Institution :
Center for Adv. Comput. Studies, Univ. of Southwestern Louisiana, Lafayette, LA, USA
Abstract :
An algorithm to map a multistage interconnection network (MIN) onto a systolic array is developed. The algorithm provides a systematic approach that lays out a cube MIN in a compact area. An area-delay analysis is presented and is compared with that of a crossbar. It is shown that the cube MIN performs better than crossbar in both area and delay
Keywords :
cellular arrays; multiprocessor interconnection networks; parallel algorithms; algorithm; area-delay analysis; compact area; crossbar; cube MIN; multistage interconnection network design; systolic array; Algorithm design and analysis; Bandwidth; Computer networks; Connectors; Costs; Delay; Multiprocessor interconnection networks; Shape; Switches; Systolic arrays;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1989. ICCD '89. Proceedings., 1989 IEEE International Conference on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-8186-1971-6
DOI :
10.1109/ICCD.1989.63408
