DocumentCode :
1975453
Title :
Pulsed-latch circuits to push the envelope of ASIC design
Author :
Paik, Seungwhun ; Shin, Youngsoo
Author_Institution :
Dept. of Electr. Eng., KAIST, Daejeon, South Korea
fYear :
2010
fDate :
22-23 Nov. 2010
Firstpage :
150
Lastpage :
153
Abstract :
The use of the slow and power-consuming flip-flops is one of the factors that cause a large gap between custom and ASIC designs. A pulsed-latch, which is a latch driven by a brief pulse clock, inherits the advantage of latch while allowing us to use a simple timing model similar to that of flip-flop. As a result, it offers the opportunity of higher performance and lower power consumption within the conventional ASIC design environment. We address challenges and problems specific to pulsed-latch ASIC, and review potential solutions. Some quantitative results are provided to assess the effectiveness of pulsed-latch circuits.
Keywords :
application specific integrated circuits; flip-flops; integrated circuit design; ASIC design; flip-flops; pulse clock; pulsed-latch circuits; timing model; Application specific integrated circuits; Clocks; Delay; Design automation; Latches; Power demand;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
SoC Design Conference (ISOCC), 2010 International
Conference_Location :
Seoul
Print_ISBN :
978-1-4244-8633-5
Type :
conf
DOI :
10.1109/SOCDC.2010.5682949
Filename :
5682949
Link To Document :
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