Novel soft error hardening design of Nanoscale CMOS latch

As CMOS technology is scaled down, the supply voltage and gate capacitance are reduced, which results in the reduction of charge storing capacity at each node and increase of the susceptibility to external noise in radiation environments. In this paper, a novel hardened latch design is proposed and compared with the previous hardened latch designs using 32nm technology node. Extensive simulation results using HSPICE are reported to show that the proposed hardened latch design achieves 15X improvement of critical charge (Qcrit) and 6X improvement of charge to power delay product ratio (QPR) compared to the most up to date hardened latch design.