Title :
System scheduling analysis for high definition multiview video encoder
Author :
Tsung, Pei-Kuei ; Ding, Li-Fu ; Chen, Wei-Yin ; Chuang, Tzu-Der ; Chien, Shao-Yi ; Chen, Liang-Gee
Author_Institution :
DSP/IC Design Lab., Nat. Taiwan Univ., Taipei, Taiwan
Abstract :
In recent years, 3D related applications, including 3D movie and 3DTV, are getting more and more attentions. In order to make the real-time 3D applications feasible, efficient multiview video coding (MVC) scheme is desired. However, the system throughput requirement on a high definition (HD) MVC encoder is at least two times higher than the current highest throughput H.264/AVC encoder design. In order to meet the target HD MVC specifications, the system scheduling analysis for the HD MVC encoder is performed in this paper. By the 8-stage MB pipeline system architecture with view-parallel MB-interleaved system scheduling and other in-core computation optimizations, the proposed HD MVC encoder design provides about 339% to 1536% higher system throughput than the previous HD H.264/AVC encoder chips and therefore the real-time HD MVC encoding can be achieved.
Keywords :
high definition video; three-dimensional television; video coding; 3D movie; 3DTV; HD MVC encoder; MB pipeline system architecture; MVC scheme; high definition multiview video encoder; in-core computation optimization; multiview video coding; system scheduling analysis; view-parallel MB-interleaved system scheduling; Automatic voltage control; Encoding; High definition video; Optimization; Pipelines; Prefetching; Throughput;
Conference_Titel :
SoC Design Conference (ISOCC), 2010 International
Conference_Location :
Seoul
Print_ISBN :
978-1-4244-8633-5
DOI :
10.1109/SOCDC.2010.5682965