DocumentCode :
1975979
Title :
Analysis of a Cascade Asymmetric Topology for Multilevel Converters
Author :
González, Sergio A. ; Valla, María I. ; Christiansen, Carlos F.
Author_Institution :
Univ. Nacional de La Plata & CONICET, La Plata
fYear :
2007
fDate :
4-7 June 2007
Firstpage :
1027
Lastpage :
1032
Abstract :
In this paper a complete analysis of a cascaded asymmetric topology for multilevel converters is presented. This topology allows to synthesize five voltage levels with a reduced number of switches and capacitors when compared to the generalized topology or the most common symmetric topologies. The converter behaves like an hybrid converter with the advantage of working with only one DC bus. It appears as a very good and simple alternative to build five level converters with minimum number of switches and only one flying capacitor per phase. The proposal is tested with Pspice simulations in a STATCOM application.
Keywords :
SPICE; cascade networks; power capacitors; static VAr compensators; switching convertors; DC bus; Pspice simulation; STATCOM application; cascade asymmetric topology; flying capacitor; high-power switches; hybrid converter; multilevel converters; Automatic voltage control; Capacitors; Frequency; Inverters; Leg; Proposals; Switches; Switching converters; Topology; Virtual colonoscopy;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Industrial Electronics, 2007. ISIE 2007. IEEE International Symposium on
Conference_Location :
Vigo
Print_ISBN :
978-1-4244-0754-5
Electronic_ISBN :
978-1-4244-0755-2
Type :
conf
DOI :
10.1109/ISIE.2007.4374739
Filename :
4374739
Link To Document :
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