DocumentCode :
1976258
Title :
Impact of low-doped substrate areas on the reliability of circuits subject to EFT events
Author :
Secareanu, Radu ; Hartin, Olin ; Feddeler, Jim ; Moseley, Richard ; Shepherd, John ; Vrignon, Bertrand ; Yang, Jian ; Li, Qiang ; Zhao, Hongwei ; Li, Waley ; Wei, Linpeng ; Salman, Emre ; Wang, Richard ; Blomberg, Dan ; Parris, Patrice
fYear :
2010
fDate :
22-23 Nov. 2010
Firstpage :
21
Lastpage :
24
Abstract :
External stresses, such as those generated due to Electrical Fast Transient (EFT) events, generate over-voltages which may result in reliability failures at the IClevel either in the form of recoverable or permanent damage of the IC. In the present paper, the relationship between the technology characteristics within a design framework and the permanent failures that such an EFT event can produce are discussed. Solutions to minimize the impact of such EFT events are presented.
Keywords :
integrated circuit reliability; semiconductor device reliability; substrates; circuit reliability failure; electrical fast transient event; external stress; low-doped substrate area; Integrated circuits; Layout; MOS devices; Reliability; Substrates; Three dimensional displays; Transient analysis;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
SoC Design Conference (ISOCC), 2010 International
Conference_Location :
Seoul
Print_ISBN :
978-1-4244-8633-5
Type :
conf
DOI :
10.1109/SOCDC.2010.5682984
Filename :
5682984
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=1976258
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