Title :
Package design for high-speed SerDes
Author :
Young, Brian ; Bhandal, Amarjit S.
Author_Institution :
ASIC Package Design, Texas Instrum., Austin, TX, USA
Abstract :
High-speed SerDes signals are significantly distorted by the time they leave the package. The distortion is caused by excess capacitive loading at points along the signal path, causing reflections. The reflections can be minimized through design modifications, added structures for compensation, filters, and characteristic impedance shifts.
Keywords :
capacitance; distortion; electric impedance; electronics packaging; filters; high-speed techniques; transmission lines; capacitive loading; compensation; filter; high-speed SerDes signal; impedance shift; package design; signal distortion; Capacitance; Electronics packaging; Impedance; Inductance; Power transmission lines; Reflection; Tuning;
Conference_Titel :
Electrical Design of Advanced Packaging & Systems Symposium (EDAPS), 2010 IEEE
Conference_Location :
Singapore
Print_ISBN :
978-1-4244-9068-4
Electronic_ISBN :
2151-1225
DOI :
10.1109/EDAPS.2010.5682990
