Implementation of systolic/wavefront processor arrays using single-chip digital signal processors

Author

Yu, Kin Hung ; Hu, Yu Hen

Author_Institution

Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA

fYear

1989

fDate

14-16 Aug 1989

Firstpage

665

Abstract

The exploitation of the high computational power and programmability of commercial single-chip digital signal processors is proposed to implement systolic/wavefront arrays. Systolic/wavefront arrays are viewed as special cases of general-purpose multiprocessing arrays and interconnection hardware which facilitates autonomous data/control communication is proposed. A prototype of a wavefront array using 4 TMS32020s, capable of performing high-speed matrix multiplication computations, is presented

Keywords

digital signal processing chips; multiprocessing systems; systolic arrays; TMS32020 processor chips; autonomous data/control communication; general-purpose multiprocessing arrays; high computational power; high-speed matrix multiplication computations; interconnection hardware; programmability; prototype; single-chip digital signal processors; systolic processor arrays; wavefront array; wavefront processor arrays; Communication system control; Concurrent computing; Digital signal processing; Digital signal processing chips; Digital signal processors; High performance computing; Parallel processing; Prototypes; Routing; Signal processing algorithms;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1989., Proceedings of the 32nd Midwest Symposium on

Conference_Location

Champaign, IL

Type

conf

DOI

10.1109/MWSCAS.1989.101942

Filename

101942