Controllable slow-wave delay line

Author

Shi, Jinglin ; Xiong, Yong-Zhong ; Hu, Sanming ; Wang, Lei ; Zhang, Bo

Author_Institution

Inst. of Microelectron., A*STAR (Agency for Sci., Technol., & Res.), Singapore, Singapore

fYear

2010

fDate

7-9 Dec. 2010

Firstpage

1

Lastpage

4

Abstract

On-chip transmission lines are basic components in millimeter-wave and terahertz circuits. In this paper, slow-wave CPW with a simple mosfet switch, ie. controllable slow-wave CPW as a controllable phase delay line are designed, characterized and analyzed in a commercial 0.18 μm CMOS process. Based on measured two-port S-parameters up to 110 GHz, the phase constants are compared at variation of the bias. It shows a continuously 15° delay over frequency range of 63 GHz to 98 GHz with a minimum insertion loss of 3.2 dB and a maximum insertion loss of 5.5 dB.

Keywords

CMOS integrated circuits; coplanar transmission lines; coplanar waveguides; field effect transistor switches; millimetre wave phase shifters; CMOS process; MOSFET switch; controllable phase delay line; controllable slow-wave delay line; frequency 63 GHz to 98 GHz; size 0.18 mum; slow-wave CPW; two-port S-parameters; CMOS integrated circuits; Coplanar waveguides; Delay lines; Dielectrics; Logic gates; Metals; Phase shifters;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical Design of Advanced Packaging & Systems Symposium (EDAPS), 2010 IEEE

Conference_Location

Singapore

ISSN

2151-1225

Print_ISBN

978-1-4244-9068-4

Electronic_ISBN

2151-1225

Type

conf

DOI

10.1109/EDAPS.2010.5683013

Filename

5683013