DocumentCode
1977045
Title
High speed DDR interface timing closure
Author
Soman, Sreekanth ; Brahme, Amit ; Patil, Mahendrasing
Author_Institution
Texas Instrum. (India) Pvt. Ltd., Bangalore, India
fYear
2010
fDate
7-9 Dec. 2010
Firstpage
1
Lastpage
4
Abstract
This paper discusses the challenges in system level timing closure of a high speed DDR interface. The different aspects of the DDR controller, I/O buffer, package and board to be modeled for ensuring stable operation at the targeted speed are described.
Keywords
DRAM chips; integrated circuit packaging; DDR controller; I/O buffer; high speed DDR interface timing closure; system level timing closure; Crosstalk; Jitter; Noise; SPICE; Strontium; Switches; Timing; DDR3; SI; SSN; crosstalk;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical Design of Advanced Packaging & Systems Symposium (EDAPS), 2010 IEEE
Conference_Location
Singapore
ISSN
2151-1225
Print_ISBN
978-1-4244-9068-4
Electronic_ISBN
2151-1225
Type
conf
DOI
10.1109/EDAPS.2010.5683019
Filename
5683019
Link To Document