Title :
Bandwidth and density reduction of tabulated data using causality checking
Author_Institution :
ASIC Package Design, Texas Instrum., Austin, TX, USA
Abstract :
A canonical interconnect model is studied to determine metrics for bandwidth and data density minimization using a causality checker for validation. It is found that insertion loss roll off to -30 dB and logarithmic data spacing with 1.1 factor spacing interval preserves good causality checker error. Wide bandwidth is needed for the causality check even for low bandwidth applications.
Keywords :
causality; integrated circuit interconnections; bandwidth reduction; canonical interconnect model; causality checker; causality checking; data density minimization; factor spacing interval; insertion loss roll; logarithmic data spacing; low bandwidth applications; tabulated data density reduction; Bandwidth; Data models; Insertion loss; Integrated circuit interconnections; Integrated circuit modeling; Measurement; Transforms;
Conference_Titel :
Electrical Design of Advanced Packaging & Systems Symposium (EDAPS), 2010 IEEE
Conference_Location :
Singapore
Print_ISBN :
978-1-4244-9068-4
Electronic_ISBN :
2151-1225
DOI :
10.1109/EDAPS.2010.5683023
