A general approach to the design of modulo N asynchronous counters with 50% duty cycle

A general technique for designing a module N asynchronous counter with 50% duty cycle output is developed using signal flow graph (SFG) analysis. One master oscillator can be used to generate several divide-by-two frequencies with 50% duty cycle outputs. This design approach eliminates the need to design a complicated circuit for synchronizing the required frequencies and also has some capability for reducing the jitter resulting from the use of two or more distinct frequencies at the same time. The suggested technique is general and straightforward and could be used to design a programmable asynchronous counter with several output frequencies