Title :
A 32k×8 radiation-hardened CMOS/SONOS EEPROM
Author :
Williams, David ; Bishop, Ruth ; Loyd, Andrew ; Adams, Dennis ; Murray, James ; Knoll, Michael
Author_Institution :
Northrop Grumman Corp., Baltimore, MD, USA
Abstract :
A 32k×8 radiation tolerant CMOS/SONOS EEPROM is described. The technology is a 1.2 micrometer radiation tolerant CMOS process into which is incorporated an oxide-nitride-oxide nonvolatile memory dielectric. This ONO dielectric, when used as the gate dielectric of an n-channel MOSFET, forms the variable threshold transistor which is the basis for the EEPROM. Charge is stored by tunneling into traps in the nitride, rather than on a floating gate as is done with most EEPROMs. No hot electron effects are used for programming or erase, so programming and erase power dissipation are quite low. The circuit was designed at Sandia National Labs and the device was fabricated by Northrop Grumman Corporation
Keywords :
CMOS memory circuits; EPROM; PLD programming; dielectric thin films; electron traps; elemental semiconductors; hole traps; integrated circuit design; integrated circuit yield; microprogramming; radiation hardening (electronics); silicon; tunnelling; 1.2 micron; 256 kbit; 32 kbit; EEPROM; ONO dielectric; Si; Si-SiO2-Si3N4-SiO2-Si; charge storage; circuit design; device fabrication; erase power dissipation; floating gate; gate dielectric; hot electron effects; n-channel MOSFET; nitride traps; oxide-nitride-oxide nonvolatile memory dielectric; programming power dissipation; radiation tolerant CMOS process; radiation tolerant CMOS/SONOS EEPROM; radiation-hardened CMOS/SONOS EEPROM; tunneling; variable threshold transistor; CMOS process; CMOS technology; Dielectrics; EPROM; Electron traps; MOSFET circuits; Nonvolatile memory; Power dissipation; SONOS devices; Tunneling;
Conference_Titel :
Nonvolatile Memory Technology Conference, 1998. 1998 Proceedings. Seventh Biennial IEEE
Conference_Location :
Albuquerque, NM
Print_ISBN :
0-7803-4518-5
DOI :
10.1109/NVMT.1998.723209
