Title :
Challenges and opportunities for circuit design in nano-scale CMOS technologies
Author_Institution :
Logic Technol. Dev., Intel Corp., Hillsboro, OR, USA
Abstract :
CMOS technology scaling trend and latest technology innovations will be discussed first. Then the paper will focus on the challenges in several critical circuit areas, including both analog and memory for high-performance microprocessors. Some innovative design solutions to enable future scaling will be discussed.
Keywords :
CMOS integrated circuits; innovation management; integrated circuit design; microprocessor chips; CMOS technology scaling; circuit areas; circuit design; high-performance microprocessors; nano-scale CMOS technology; technology innovation; Analog circuits; CMOS integrated circuits; CMOS technology; Phase locked loops; Program processors; Technological innovation; Transistors;
Conference_Titel :
ESSCIRC (ESSCIRC), 2012 Proceedings of the
Conference_Location :
Bordeaux
Print_ISBN :
978-1-4673-2212-6
Electronic_ISBN :
1930-8833
DOI :
10.1109/ESSCIRC.2012.6341248
