Title :
Notice of Retraction
Design and realization of three phase three-level inverter based on DSP&FPGA
Author :
Peide Sun ; Wei Jiang ; Peng Yi
Author_Institution :
Inf. Sci. & Technol., Donghua Univ., Shanghai, China
Abstract :
Notice of Retraction
After careful and considered review of the content of this paper by a duly constituted expert committee, this paper has been found to be in violation of IEEE´s Publication Principles.
We hereby retract the content of this paper. Reasonable effort should be made to remove all past references to this paper.
The presenting author of this paper has the option to appeal this decision by contacting TPII@ieee.org.
Firstly, in this paper, the topological structure and the principle of the three-level NPC inverter are analyzed, by using the SVPWM, controlling the mid-point drift in voltage-dividing capacitor, then/and generating the three-level voltage output. Secondly, the method of the combined programming of DSP and FPGA is used for the experimental platform, which realizes the reasonable distribution and utilization of the hardware resources, and increases the speed and accuracy of the control. Finally, the feasibility of the method is proved by the simulation and experiment.
Keywords :
digital signal processing chips; field programmable gate arrays; invertors; power capacitors; DSP; FPGA; SVPWM; accuracy control; hardware resources; speed control; three phase three-level inverter; three-level NPC inverter; voltage-dividing capacitor; Digital signal processing; Field programmable gate arrays; Insulated gate bipolar transistors; Inverters; Random access memory; Space vector pulse width modulation; DSP; FPGA; SVPWM; Three-level Inverter;
Conference_Titel :
Electrical and Control Engineering (ICECE), 2011 International Conference on
Conference_Location :
Yichang
Print_ISBN :
978-1-4244-8162-0
DOI :
10.1109/ICECENG.2011.6057298
