Title :
Nanowire and planar UTB SOI Schottky Barrier MOSFETs with dopant segregation
Author :
Knoll, L. ; Schäfer, A. ; Trellenkamp, S. ; Bourdelle, K.K. ; Zhao, Q.T. ; Mantl, S.
Author_Institution :
Peter-Grunberg-Inst. (PGI 9-IT), JARA-FIT Forschungszentrum, Mülich, Germany
Abstract :
Schottky Barrier MOSFETs were fabricated on ultra thin body (UTB) SOI with planar and NW-array device geometry. Implantation into Silicide (IIS) was used to lower the Schottky Barrier height for n- and p-type MOSFETs. The enhanced gate control of the NW array reduces Drain Induced Barrier Lowering (DIBL) and improves the subthreshold slope in n-type MOSFETs, whereas the corrected current drops. In p-type MOSFETs on current and Ion/Ioff ratio is enhanced.
Keywords :
MOSFET; Schottky barriers; nanowires; silicon-on-insulator; dopant segregation; drain induced barrier lowering; n-type MOSFET; nanowire UTB SOI Schottky barrier MOSFET; p-type MOSFET; planar UTB SOI Schottky barrier MOSFET; silicide; ultra thin body SOI; Arrays; Hafnium compounds; Logic gates; MOSFETs; Schottky barriers; Silicides; Silicon; Implantation into silicide; Nanowire Schottky Barrier MOSFETs; NiSi2;
Conference_Titel :
Ultimate Integration on Silicon (ULIS), 2012 13th International Conference on
Conference_Location :
Grenoble
Print_ISBN :
978-1-4673-0191-6
Electronic_ISBN :
978-1-4673-0190-9
DOI :
10.1109/ULIS.2012.6193353
