VEasy: A tool suite for teaching VLSI functional verification

Author

Pagliarini, Samuel Nascimento ; Kastensmidt, Fernanda Lima

Author_Institution

Programas de Pos-Grad. em Microeletronica (PGMICRO) e Comput. (PPGC), Inst. de Inf. - UFRGS, Porto Alegre, Brazil

fYear

2011

fDate

5-6 June 2011

Firstpage

94

Lastpage

97

Abstract

This paper describes a tool suite aimed at Functional Verification (FV) teaching in the context of VLSI circuits. FV is considered a major bottleneck in design cycles and one of the reasons is the lack of proper training. Therefore teaching it at the undergraduate or graduate levels is an important issue. This paper presents VEasy and describes the features that allow for lint analysis, simulation, data generation by a Graphical User Interface, checking and coverage collection and analysis. All these features merge together to create a complete verification environment, which is appropriated for teaching several concepts of FV.

Keywords

VLSI; electronic engineering computing; electronic engineering education; graphical user interfaces; teaching; GUI; VEasy; VLSI circuits; VLSI functional verification teaching; checking collection; coverage collection; data generation; graphical user interface; lint analysis; tool suite; Analytical models; Complexity theory; Education; Graphical user interfaces; Hardware design languages; Industries; Measurement; Functional Verification; VLSI teaching; coverage analysis; dynamic verification; testbench creation;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronic Systems Education (MSE), 2011 IEEE International Conference on

Conference_Location

San Diego, CA

Print_ISBN

978-1-4577-0548-9

Electronic_ISBN

978-1-4577-0550-2

Type

conf

DOI

10.1109/MSE.2011.5937102

Filename

5937102