Title :
Impact of local back biasing on performance in hybrid FDSOI/bulk high-k/metal gate low power (LP) technology
Author :
Fenouillet-Beranger, C. ; Perreau, P. ; Benoist, T. ; Richier, C. ; Haendler, S. ; Pradelle, J. ; Bustos, J. ; Brun, P. ; Tosti, L. ; Weber, O. ; Andrieu, F. ; Orlando, B. ; Pellissier-Tanon, D. ; Abbate, F. ; Pvichard, C. ; Beneyton, R. ; Gregoire, M. ;
Author_Institution :
LETI, CEA, Grenoble, France
Abstract :
In this paper, we study how to boost the performance of FDSOI devices with High-K and Single Metal gate by using the combination of UTBOX GP and local back biasing integrated with our hybrid process. The interest of local back biasing is highlighted in term of VT modulation and power management study on the 45 nm 0.374 μm2 bitcells and on the ESD functionality as compared to bulk technology.
Keywords :
silicon-on-insulator; bulk technology; hybrid FDSOI device; local back biasing; metal gate low power technology; modulation; power management; single metal gate; Electrostatic discharges; Films; Logic gates; MOS devices; Performance evaluation; Substrates; Transistors;
Conference_Titel :
Ultimate Integration on Silicon (ULIS), 2012 13th International Conference on
Conference_Location :
Grenoble
Print_ISBN :
978-1-4673-0191-6
Electronic_ISBN :
978-1-4673-0190-9
DOI :
10.1109/ULIS.2012.6193383
