Title :
Compact (Wg/Lg=80/85nm) FDSOI 1T-DRAM programmed by Meta Stable Dip
Author :
Romanjek, K. ; Andrieu, F. ; Cluzel, J. ; Brevard, L. ; Perreau, P. ; Tabone, C. ; Guegan, G. ; Poiroux, T.
Author_Institution :
CEA-Leti, Grenoble, France
Abstract :
We demonstrate one of the most compact 1 Transistor DRAM (1T-DRAM) cell on Ultra-Thin-Body and 25nm thin Buried oxide (UTBB) down to a gate width of Wg=80nm and length of Lg=35nm for embedded DRAM applications. We have optimized the programming voltages and studied the influence of the device geometry (Wg, Lg) on the 1T-DRAM performance. The Meta Stable Dip (MSD) method provides high read current margin values, reaching 224μA/μm. This is the first experimental assessment of the MSD approach on such scaled 1T-DRAMs.
Keywords :
DRAM chips; elemental semiconductors; geometry; silicon; silicon-on-insulator; transistors; MSD programming method; Si; UTBB; compact FDSOI 1 transistor DRAM cell; compact FDSOI 1T-DRAM cell; current margin value; device geometry; metastable dip programming method; programming voltage optimization; size 25 nm; size 35 nm; size 80 nm; ultrathin-body buried oxide;
Conference_Titel :
Ultimate Integration on Silicon (ULIS), 2012 13th International Conference on
Conference_Location :
Grenoble
Print_ISBN :
978-1-4673-0191-6
Electronic_ISBN :
978-1-4673-0190-9
DOI :
10.1109/ULIS.2012.6193392
