A programmable calibration/BIST engine for RF/analog blocks in SoCs

Author

Hermosillo, J. ; Carballido, J. ; Veloz, A. ; Arditti, D. ; Del Rio, A. ; Borrayo, E. ; Guzman, M.E. ; Lakdawala, H. ; Verhelst, M.

Author_Institution

Syst. Integration & Adaptivity, Intel Labs., Guadalajara, Mexico

fYear

2012

fDate

17-21 Sept. 2012

Firstpage

133

Lastpage

136

Abstract

A programmable digital engine for RF/analog on/off-line calibration and Built-in Self-Test (BIST) enables a new level of robustness and portability for mixed signal SoCs. The drop-in IP-block is based on a dedicated CPU with data path and instruction set extensions optimized for the compute intensive RF calibration algorithms. The concept is demonstrated with an implementation in a 32nm SoC test chip where the 0.63mm² engine has been fully integrated with a WiFi radio and has been used to measure and calibrate its inherent non-idealities and to evaluate its performance.

Keywords

built-in self test; calibration; system-on-chip; wireless LAN; BIST engine; IP-block; RF/analog blocks; RF/analog on/off-line calibration; SoC; WiFi radio; built-in self-test; programmable calibration; programmable digital engine; Built-in self-test; Calibration; Engines; IEEE 802.11 Standards; Quadrature amplitude modulation; Radio frequency; System-on-a-chip;

fLanguage

English

Publisher

ieee

Conference_Titel

ESSCIRC (ESSCIRC), 2012 Proceedings of the

Conference_Location

Bordeaux

ISSN

1930-8833

Print_ISBN

978-1-4673-2212-6

Electronic_ISBN

1930-8833

Type

conf

DOI

10.1109/ESSCIRC.2012.6341307

Filename

6341307