Title :
The design of the conrtoller based on the verilog HDL language
Author :
Zhang, Ming ; Liu, Hao Ting
Author_Institution :
Dept. of Electron. Inf. Sci. & Technol., Shen Yang Univ., Shenyang, China
Abstract :
This design uses the verilog HDL to devise an RISC CPU, which can simplify the instruction system to make the structure of the computer more simple and reasonable. The difference between the RISC CPU and the ordinary CPU is :Its timing control signal components are achieved by the hardwire logic instead of the microprogram control. So its creating speed of the control sequence is much faster than those which use the microprogram control.
Keywords :
hardware description languages; reduced instruction set computing; RISC CPU; Verilog HDL language; hardware description language; hardwire logic; instruction system; microprogram control; Educational institutions; Hardware design languages; Information science; Random access memory; Read only memory; Reduced instruction set computing; Timing; MAX+PLUS II; RISC CPU; Simulation; Verilog Language;
Conference_Titel :
Electrical and Control Engineering (ICECE), 2011 International Conference on
Conference_Location :
Yichang
Print_ISBN :
978-1-4244-8162-0
DOI :
10.1109/ICECENG.2011.6057361
