DocumentCode
1979715
Title
A 65nm SRAM achieving 250mV retention and 350mV, 1MHz, 55fJ/bit access energy, with bit-interleaved radiation Soft Error tolerance
Author
Clerc, Sylvain ; Abouzeid, Fady ; Gasiot, Gilles ; Gauthier, David ; Roche, Philippe
Author_Institution
STMicroelectron., Crolles, France
fYear
2012
fDate
17-21 Sept. 2012
Firstpage
313
Lastpage
316
Abstract
An Ultra Low Voltage memory was fabricated in 65nm CMOS with an optimized 10 transistors bitcell. It withstands 1.2V down to 0.35V voltage range, achieves 55fJ/bit energy access at 0.35V and exhibits wafer level yield above 95% at 0.4V, 1MHz. Packaged parts test show 0.32V minimum operating voltage at 500kHz, up to 17X energy gain per operation and 250mV retention voltage at 125°C. The memory terrestrial radiation Soft Error Rate was characterized with no multibit errors reported, enabling radiation reliability through bit-interleaving combined with error correcting code.
Keywords
CMOS memory circuits; SRAM chips; error correction codes; radiation hardening (electronics); transistors; CMOS; SRAM; bit-interleaved radiation soft error tolerance; error correcting code; frequency 1 MHz; memory terrestrial radiation soft error rate; radiation reliability; size 65 nm; transistors bitcell; ultra low voltage memory; voltage 250 mV; voltage 350 mV; Error correction codes; Logic gates; Multiplexing; Random access memory; Temperature measurement; Transistors;
fLanguage
English
Publisher
ieee
Conference_Titel
ESSCIRC (ESSCIRC), 2012 Proceedings of the
Conference_Location
Bordeaux
ISSN
1930-8833
Print_ISBN
978-1-4673-2212-6
Electronic_ISBN
1930-8833
Type
conf
DOI
10.1109/ESSCIRC.2012.6341317
Filename
6341317
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