• DocumentCode
    1979948
  • Title

    2.1 Times increase of drain efficiency by dual supply voltage scheme in 315MHz class-F Power amplifier at output power of −20dBm

  • Author

    Iguchi, Shunta ; Saito, Akira ; Watanabe, Kazunori ; Sakurai, Takayasu ; Takamiya, Makoto

  • Author_Institution
    Univ. of Tokyo, Tokyo, Japan
  • fYear
    2012
  • fDate
    17-21 Sept. 2012
  • Firstpage
    345
  • Lastpage
    348
  • Abstract
    Dual power supply voltage (VDD) scheme is proposed to increase the efficiency of a power amplifier (PA) with small output power (POUT) for short-range wireless sensor networks (e.g. body area networks). At POUT of -20dBm, compared with the conventional single VDD PA, the drain efficiency (DE) and the global efficiency (GE) of the proposed dual VDD PA increase by 2.1 times and 1.5 times, respectively. A class-F PA fabricated in 40-nm CMOS with the proposed dual VDD (0.2V and 0.56V) achieves the highest DE of 42% at POUT of -20dBm in the published PA´s. The PA is applied to a 315MHz OOK transmitter (TX) and the TX achieves the highest GE of 28% at POUT of -20dBm and the lowest energy of 36pJ/bit (= 36μW@1Mbps) in the published TX´s.
  • Keywords
    amplitude shift keying; power amplifiers; transmitters; OOK transmitter; class-F power amplifier; drain efficiency; dual power supply voltage; frequency 315 MHz; CMOS integrated circuits; Mixers; Power amplifiers; Power demand; Power generation; Transistors; Wireless sensor networks;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    ESSCIRC (ESSCIRC), 2012 Proceedings of the
  • Conference_Location
    Bordeaux
  • ISSN
    1930-8833
  • Print_ISBN
    978-1-4673-2212-6
  • Electronic_ISBN
    1930-8833
  • Type

    conf

  • DOI
    10.1109/ESSCIRC.2012.6341325
  • Filename
    6341325