Damageless sputter deposition for metal gate CMOS technology

Author

Takeuchi, H. ; Min She ; Watanabe, K. ; Tsu-Jae King

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA

fYear

2003

fDate

23-25 June 2003

Firstpage

35

Lastpage

36

Abstract

In this paper, it is demonstrated that excellent gate-oxide integrity can be achieved in Mo-gated MOSFETs fabricated using a conventional process flow, by eliminating high-energy particle bombardment during the gate sputtering process. P-channel MOSFETs were fabricated using a conventional process with reasonably thin gate oxide (2.5 nm thermal SiO/sub 2/), and source/drain formation by BF/sub 2+/ implantation (15 keV, 3/spl times/10/sup 15/ cm/sup -2/) followed by a 950/spl deg/C, 1 minute rapid thermal anneal. Three different gate materials (150 nm thick) were studied. Mo sputtered without the PCT, Mo sputtered with the PCT, and LPCVD p/sup +/ poly-Si.

Keywords

MOSFET; elemental semiconductors; ion implantation; molybdenum; rapid thermal annealing; semiconductor thin films; silicon; silicon compounds; sputter deposition; 1 min; 15 keV; 150 nm; 2.5 nm; 950 degC; BF/sub 2+/ implantation; LPCVD; Mo-SiO/sub 2/-SiN-SiO/sub 2/-Si; Mo-gated MOSFET; damageless sputter deposition; gate sputtering process; high-energy particle bombardment; low pressure chemical vapor deposition; metal gate CMOS technology; p-channel MOSFET; plasma charge trap; rapid thermal annealing; source/drain formation; thin gate oxide; CMOS technology; Capacitors; Dielectric materials; Electric breakdown; Inorganic materials; Leakage current; MOSFETs; Rapid thermal annealing; Rapid thermal processing; Sputtering;

fLanguage

English

Publisher

ieee

Conference_Titel

Device Research Conference, 2003

Conference_Location

Salt Lake City, UT, USA

Print_ISBN

0-7803-7727-3

Type

conf

DOI

10.1109/DRC.2003.1226859

Filename

1226859