Automata implementation into FPGAs with multiple encoding of microinstructions

The method of synthesis and implementation of Mealy finite state machines into FPGAs is proposed in this article. Synthesis method is based on the architectural decomposition of logic circuit of automaton and multiple encoding of microinstruction executed by implemented control algorithm. All microinstructions are divided into subsets based on a current state. Then, they are encoded separately in each subset. It means that each microinstruction is represented as a code of current state and code of microinstruction from adequate subset. Microinstructions are decoded in the second-level circuit based on the multiple code and the code of a current state. Because the length of the multiple code of microinstruction is relatively short the number of logic functions realized by the combinational circuit of first-level is. It leads to implementation of logic circuit of automaton in double-level structure where utilization of both, LUTs and embedded memory blocks of FPGA device, is applied. The combinational circuit and the register are implemented with use of LUTs, like in standard realizations. While, the decoder is implemented with use of memory blocks. Such realization leads to balanced and rational usage of hardware resources of modern FPGA devices.