New BIST scheme and 3-D generic diagnostic algorithm for nano-scale devices

Author

Elbably, Mohamed

Author_Institution

Fac. of Eng., Dept. of Electron., Commun. & Comput. Eng., Helwan Univ., Cairo, Egypt

fYear

2013

fDate

19-20 Aug. 2013

Firstpage

369

Lastpage

374

Abstract

To test and diagnose the nano-scale devices a new test scheme and diagnostic generic algorithm for three directions (3-D) will be presented. Isolate any faulty block(s) and preventing the fault effect propagation among the nano-devices is the major challenges for these new nano-devices. In this research, a new built-in self-test (BIST) scheme will be proposed using different modes with two test configurations to test any selected block(s) in nano devices. Also, based on results of the proposed BIST scheme, a generic 3-D diagnostic algorithm to identify the faulty and fault-free blocks will be presented. An practical analysis to evaluate the average amount of hardware and time required for the proposed algorithm will be presented.

Keywords

built-in self test; electronic design automation; fault diagnosis; field programmable gate arrays; logic testing; nanoelectromechanical devices; 3D generic diagnostic algorithm; BIST scheme; built-in self-test scheme; fault effect propagation; fault-free block identification; faulty block identification; faulty block isolation; nanoscale devices; Algorithm design and analysis; Built-in self-test; Circuit faults; Fault diagnosis; Field programmable gate arrays; Nanoscale devices; Registers; Electronics design automation (EDA); diagnostic and generic algorithm design for digital systems; testing;

fLanguage

English

Publisher

ieee

Conference_Titel

System Engineering and Technology (ICSET), 2013 IEEE 3rd International Conference on

Conference_Location

Shah Alam

Print_ISBN

978-1-4799-1028-1

Type

conf

DOI

10.1109/ICSEngT.2013.6650202

Filename

6650202