Title :
A novel process for co-integration of vertical double-gate and planar single-gate MOSFETs
Author :
Masahara, M. ; Matsukawa, T. ; Hosokawa, S. ; Ishii, K. ; Yongxun Liu ; Tanoue, H. ; Sakamoto, K. ; Sekigawa, T. ; Yamauchi, H. ; Kanemaru, S. ; Suzuki, E.
Author_Institution :
Nanoelectron. Res. Inst., Nat. Inst. of Adv. Ind. Sci. & Technol., Tsukuba, Japan
Abstract :
In this paper, we demonstrates a novel process for the co-integration to maximize the circuit design simplicity and circuit performance.
Keywords :
MOSFET; integrated circuit design; circuit designing; double-gate MOSFET; planar single-gate MOSFET; CMOS technology; Circuit optimization; Circuit synthesis; Etching; Ion implantation; MOSFETs; Manufacturing industries; Nanoelectronics; Scalability; Virtual colonoscopy;
Conference_Titel :
Device Research Conference, 2003
Conference_Location :
Salt Lake City, UT, USA
Print_ISBN :
0-7803-7727-3
DOI :
10.1109/DRC.2003.1226866
