A Low-Power Low-Phase-Noise CMOS VCO using RF SiP Technology

Author

Ohashi, Kazumi ; Ito, Yu ; Ito, H. ; Okada, Kenichi ; Hatakeyama, H. ; Ozawa, Nobuki ; Sato, Mitsuhisa ; Aizawa, Takehiro ; Ito, Takao

Author_Institution

Precision & Intell. Lab., Integrated Res. Inst., Yokohama

fYear

2007

fDate

11-14 Dec. 2007

Firstpage

1

Lastpage

4

Abstract

This paper presents a feasibility study on VCO using RF SiP technology, which is an RF application of stacked SiP. An off-chip inductor is implemented in a separated chip, and measured Q factor is 130. A phase noise is -119 dBc/Hz at 1 MHz offset for a 5.84-GHz carrier frequency, and frequency tuning range is 5.73 GHz-5.95 GHz. Power consumption is 1.93 mW, and 180 nm CMOS process is utilized. FOM is -192dBc/Hz.

Keywords

CMOS integrated circuits; Q-factor; low-power electronics; phase noise; radiofrequency integrated circuits; silicon compounds; voltage-controlled oscillators; CMOS; Q factor; RF technology; SiP; VCO; frequency 5.73 GHz to 5.95 GHz; frequency 5.84 GHz; low phase noise; low power; off chip inductor; power 1.93 mW; size 180 nm; CMOS technology; Energy consumption; Inductors; Phase noise; Q factor; Q measurement; Radio frequency; Semiconductor device measurement; Tuning; Voltage-controlled oscillators; CMOS; LC-VCO; RF SiP technology; high-Q inductor; low phase noise; low power;

fLanguage

English

Publisher

ieee

Conference_Titel

Microwave Conference, 2007. APMC 2007. Asia-Pacific

Conference_Location

Bangkok

Print_ISBN

978-1-4244-0748-4

Electronic_ISBN

978-1-4244-0749-1

Type

conf

DOI

10.1109/APMC.2007.4555023

Filename

4555023