Dynamic Reconfigurable Si CMOS VCO Using a Transmission-Line Resonator with PMOS-Bias and PMOS-Crosscouple Topology

Author

Ito, Takeshi ; Chaivipas, Win ; Okada, Kenichi ; Matsuzawa, Akira

Author_Institution

Dept. of Phys. Electron., Tokyo Inst. of Technol., Tokyo

fYear

2007

fDate

11-14 Dec. 2007

Firstpage

1

Lastpage

4

Abstract

This paper proposes a low-phase noise CMOS VCO for more than 10 GHz oscillation, which utilizes a PMOS-bias and PMOS-crosscouple topology. PMOS transistors have lower 1/f noise while they have larger gate capacitance. In this work, a transmission-line resonator is employed to enhance the high-frequency operation. The VCO is fabricated by a 180 nm Si CMOS process. A phase noise is -112.6 dBc/Hz, and frequency tuning range is 11.8 GHz-12.4 GHz. Power consumption is 8.6 mW. Figure of merit is -184.9 dBc/Hz.

Keywords

1/f noise; CMOS integrated circuits; elemental semiconductors; microwave oscillators; network topology; phase noise; silicon; voltage-controlled oscillators; 1/f noise; PMOS transistors; PMOS-bias topology; PMOS-crosscouple topology; Si; Si CMOS VCO; Si CMOS process; dynamic reconfigurable VCO; frequency 11.8 GHz to 12.4 GHz; high-frequency operation; phase noise; power 8.6 mW; power consumption; size 180 nm; transmission-line resonator; CMOS process; Capacitance; Energy consumption; Frequency; MOSFETs; Phase noise; Topology; Transmission lines; Tuning; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Microwave Conference, 2007. APMC 2007. Asia-Pacific

Conference_Location

Bangkok

Print_ISBN

978-1-4244-0748-4

Electronic_ISBN

978-1-4244-0749-1

Type

conf

DOI

10.1109/APMC.2007.4555025

Filename

4555025