Title :
A 576 Mb DRAM with 16-channel 10.3125Gbps serial I/O and 14.5 ns latency
Author :
Vamvakos, Socrates D. ; Kleveland, Bendik ; Sikdar, Debabrata ; Ahuja, B.K. ; Lin, Huiming ; Balachandran, Jayaprakash ; Balakrishnan, W. ; Bottelli, Aldo ; Chen, Jiann-Jong ; Chen, Xia ; Choi, Jang-Young ; Choi, Jang-Young ; Chopra, R. ; Dabral, Shashank
Author_Institution :
MoSys Inc., Santa Clara, CA, USA
Abstract :
A 576 Mb DRAM is implemented with 16 serial links at 10.3125Gbps. Using careful memory/SerDes/package co-design, the system achieves 14.5ns latency and 24.75GByte/s read/write bandwidth. It achieves SRAM-like random access by using logic-compatible 65nm GP embedded DRAM and small 36 Kb sub-arrays with hidden refresh.
Keywords :
electronics packaging; random-access storage; 16-channel serial I/O; SRAM-like random access; logic-compatible GP embedded DRAM; memory/SerDes/package codesign; read/write bandwidth; serial links; size 65 nm; Clocks; Jitter; Phase locked loops; Random access memory; Receivers; System-on-a-chip; Voltage-controlled oscillators;
Conference_Titel :
ESSCIRC (ESSCIRC), 2012 Proceedings of the
Conference_Location :
Bordeaux
Print_ISBN :
978-1-4673-2212-6
Electronic_ISBN :
1930-8833
DOI :
10.1109/ESSCIRC.2012.6341354
