A 16nm SRAM design for low power and high read stability

SRAM memory design in nanoscale regime has become increasingly challenging due to the reducing noise margins and increased sensitivity to threshold voltage variations. To overcome these challenges, different memory cells have been proposed for SRAMs with different transistor structures. These designs improve the cell stability in the subthreshold regime but suffer from bitline leakage noise, placing constraints on the number of cells shared by each bitline. In this paper, we propose a novel 11T SRAM cell topology which achieves cell stability as well as prevents bitline leakage. In addition to that, the proposed cell shows appreciable improvement in the dynamic power consumption. The HSPICE simulation and analysis at a 16nm feature size in CMOS process shows that the bitline leakage power consumption of the proposed 11T SRAM cell is reduced by 38% and the dynamic power consumption is reduced by 54% when compared to the existing 10T SRAM cell, while maintaining the read static noise margin nearly twice that of conventional 6T SRAM circuit.