Title :
Silicon nano-transistors and breaking the 10 nm physical gate length barrier
Author :
Chau, R. ; Doyle, B. ; Doczy, M. ; Datta, S. ; Hareland, S. ; Jin, B. ; Kavalieros, J. ; Metz, M.
Author_Institution :
Components Res., Intel Corp., Hillsboro, OR, USA
Abstract :
In this paper, the performance and energy delay trends for research devices down to 10 nm and also discusses the 10 nm barrier and potential ways to break it were explored.
Keywords :
CMOS integrated circuits; MOSFET; dielectric materials; elemental semiconductors; nanostructured materials; silicon; silicon compounds; 10 nm; CMOS integrated circuits; MOSFET; Si; SiO/sub 2/; energy delay; gate length barrier; silicon nanotransistors; CMOS technology; Delay; Laboratories; Lifting equipment; Logic devices; Manufacturing; Microprocessors; Production; Silicon; Transistors;
Conference_Titel :
Device Research Conference, 2003
Conference_Location :
Salt Lake City, UT, USA
Print_ISBN :
0-7803-7727-3
DOI :
10.1109/DRC.2003.1226901
