DocumentCode :
1980990
Title :
Abstraction from counters: an application on real-time systems
Author :
Logothetis, G. ; Schneider, K.
Author_Institution :
Inst. fur Rechnerentwurf und Fehlertoleranz, Karlsruhe Univ., Germany
fYear :
2000
fDate :
2000
Firstpage :
486
Lastpage :
493
Abstract :
We present abstraction techniques for systems containing counters, which allow us to significantly reduce their state spaces for their efficient verification. In contrast to previous approaches, our abstraction technique lifts the entire verification problem, i.e., also the specification, to the abstract level. As an application, we consider the reduction of real-time systems by replacing discrete clocks of timed automata with abstract counters. The presented method allows the reduction of such systems to very small state spaces. As benchmark examples, we consider the generalized railroad crossing and Fischer´s mutual exclusion protocol
Keywords :
counting circuits; finite state machines; formal verification; logic CAD; real-time systems; FSM; abstraction techniques; counters; discrete clocks replacement; real-time systems; specification; state spaces reduction; timed automata; Automata; Clocks; Computer languages; Concrete; Counting circuits; Explosions; Formal verification; Page description languages; Real time systems; State-space methods;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design, Automation and Test in Europe Conference and Exhibition 2000. Proceedings
Conference_Location :
Paris
Print_ISBN :
0-7695-0537-6
Type :
conf
DOI :
10.1109/DATE.2000.840829
Filename :
840829
Link To Document :
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