Title :
Sub-10-ps gate delay by reducing the current crowding effect at an extension
Author :
Hisamoto, D. ; Umeda, K. ; Ohnishi, K. ; Yugami, J. ; Ushiyama, M. ; Shiba, T.
Author_Institution :
Central Res. Lab., Hitachi Ltd., Kokubunji, Japan
Abstract :
In short-channel CMOS devices with extension structures, current crowding was found to occur in the source extension, significantly degrading current drivability. Reducing this effect by using high-dose extensions and low parasitic capacitance provided by a localized punchthrough stopper layer produced high drivability, enabling a sub-10-ps CMOS gate delay to be attained.
Keywords :
CMOS integrated circuits; MOSFET; capacitance; delays; rapid thermal processing; semiconductor process modelling; 10 ps; current crowding effect; current drivability; extension structures; gate delay; high-dose extensions; localized punchthrough stopper layer; parasitic capacitance; short-channel CMOS devices; source extension; CMOS process; Current density; Delay effects; Dielectrics; Electrodes; Impurities; Lithography; MOS devices; Parasitic capacitance; Proximity effect;
Conference_Titel :
Electron Devices Meeting, 1997. IEDM '97. Technical Digest., International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-4100-7
DOI :
10.1109/IEDM.1997.650363
