• DocumentCode
    1981097
  • Title

    Clocktree RLC extraction with efficient inductance modeling

  • Author

    Chang, Norman ; Lin, Shen ; He, Lei ; Nakagawa, O. Sam ; Xie, Weize

  • Author_Institution
    Hewlett-Packard Labs., Palo Alto, CA, USA
  • fYear
    2000
  • fDate
    2000
  • Firstpage
    522
  • Lastpage
    526
  • Abstract
    In this paper we present an efficient yet accurate inductance extraction methodology and also apply it to clocktree RLC extraction. We first show that without loss of accuracy, the inductance extraction problem of n traces with or without ground planes can be reduced to a number of one-trace and two-trace subproblems. We then solve one-trace and two-trace subproblems via a table-based approach. We finally validate the linear cascading assumption that enables us to apply our inductance extraction approach to clocktree RLC extraction and optimization
  • Keywords
    digital integrated circuits; inductance; integrated circuit interconnections; integrated circuit layout; integrated circuit modelling; clocktree RLC extraction; inductance extraction methodology; inductance modeling; linear cascading assumption; one-trace subproblems; table-based approach; two-trace subproblems; Clocks; Conductivity; Delay; Frequency; Helium; Inductance; Laboratories; Routing; Signal design; Wires;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design, Automation and Test in Europe Conference and Exhibition 2000. Proceedings
  • Conference_Location
    Paris
  • Print_ISBN
    0-7695-0537-6
  • Type

    conf

  • DOI
    10.1109/DATE.2000.840835
  • Filename
    840835