Architectural Power Estimation Technique for IP-Based System-on-Chip

In this paper, we present an architectural power estimation technique for register transfer level. The proposed methodology allows to estimate the power dissipation on digital systems composed of intellectual property (IP) components by using the statistical knowledge of their primary inputs. During the power estimation procedure, the sequence of an input stream is generated by a genetic algorithm (GA) using input metrics. Then, a Monte Carlo zero delay simulation is performed and a power dissipation macromodel function is built from power dissipation results. From then on, this macromodel function can be used to estimate power dissipation of the system just by using the statistics of the IPs primary inputs. In our experiments with the test IP system, the average error is 29.63%.