On the design of a Fail Stop Microcontroller

This paper describes the FPGA design of a partially Fail-Stop 8 bit RISC microcontroller. After core implementation, the spare resources in FPGA devices can be used to implement Fault Detection blocks in the seek of a Fault Coverage as high as possible, having always present the logic cell occupation limit. The individual analysis of core components rated a group of entities by fault probability, and Fault Detection methods were implemented for 3 of them. The result is a logic activity Fault Coverage of about 70 %, obtained with an Logic Cell overhead of only 45%, and a system FIT (Failures in Time) improvement of 143%.