Architectural power optimization by bus splitting

Author

Hsieh, Cheng-Ta ; Pedram, Massoud

Author_Institution

Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA

fYear

2000

fDate

2000

Firstpage

612

Lastpage

616

Abstract

A split-bus architecture is proposed to improve the power dissipation for global data exchange among a set of modules. The resulting bus splitting problem is formulated and solved combinatorially. Experimental results show that the power saving of the split-bus architecture compared to the monolithic-bus architecture varies from 16% to 50%, depending on the characteristics of the data transfer among the modules and the configuration of the split bus. The proposed split-bus architecture can be extended to multi-way split-bus when a large number of modules are to be connected

Keywords

application specific integrated circuits; circuit optimisation; integrated circuit design; integrated circuit interconnections; low-power electronics; SOC design; architectural power optimization; bus splitting; data transfer characteristics; global data exchange; multiway split-bus; split-bus architecture; Bandwidth; Bidirectional control; Capacitance; Energy consumption; Microprocessors; Power dissipation; Resource management; Signal design; System-on-a-chip; Wires;

fLanguage

English

Publisher

ieee

Conference_Titel

Design, Automation and Test in Europe Conference and Exhibition 2000. Proceedings

Conference_Location

Paris

Print_ISBN

0-7695-0537-6

Type

conf

DOI

10.1109/DATE.2000.840848

Filename

840848