Implementation and testing of multipliers using reversible logic

Reversible logic gates are very much in demand for the future computing technologies as they are known to produce zero power dissipation under ideal conditions. Reversible logic circuits are of interests to power minimization having applications in low power CMOS design, optical information processing DNA computing, bio informatics, quantum computing and nanotechnology. Both reversible logic synthesis and testing reversible logic circuits are very important issues in this area. Multipliers are very essential for the construction of various computational units of a quantum computer. Multiplier is an important hardware unit that decides the speed in any processor. In this work, an unsigned four bit array multiplier and signed Baugh-Wooley multiplier circuits using reversible gates are implemented. A reversible Built In Logic Block Observer (BILBO) is also designed by using which the proposed reversible multiplier circuits are tested for Stuck-at faults (SAF) and missing gate faults (MGF) based on signature analysis.