DocumentCode
1981730
Title
Cost and benefit models for logic and memory BIST
Author
Lu, Juin-Ming ; Wu, Cheng-Wen
Author_Institution
Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
fYear
2000
fDate
2000
Firstpage
710
Lastpage
714
Abstract
We present cost and benefit models and analyze the economics effects of built-in self-test (BIST) for logic and memory cores. In our cost and benefit models for BIST, we take into consideration the design verification time and test development time associated with testability. Experimental results for logic BIST and memory BIST examples show that a threshold volume exists when BIST is profitable for the logic core under consideration - it is not recommended for a higher volume. However, BIST is a good choice for memory cores in general
Keywords
built-in self test; cost-benefit analysis; integrated circuit economics; integrated circuit testing; integrated logic circuits; integrated memory circuits; built-in self-test; cost-benefit models; design verification time; economics effects; logic BIST; logic cores; memory BIST; memory cores; profitability; test development time; threshold volume; Built-in self-test; Cost benefit analysis; Design for testability; Electrical capacitance tomography; Logic; Product development; Prototypes; System testing; System-on-a-chip; Time to market;
fLanguage
English
Publisher
ieee
Conference_Titel
Design, Automation and Test in Europe Conference and Exhibition 2000. Proceedings
Conference_Location
Paris
Print_ISBN
0-7695-0537-6
Type
conf
DOI
10.1109/DATE.2000.840865
Filename
840865
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