Title :
Improving the schedule quality of static-list time-constrained scheduling
Author :
Govindarajan, Sriram ; Vemari, R.
Author_Institution :
Dept. of Electr. & Comput. Eng., Cincinnati Univ., OH, USA
Abstract :
Summary form only given. The most compelling reason for High-Level Synthesis (HLS) to be accepted in the state-of-the-art CAD flow is its ability to perform design space exploration. Design space exploration requires efficient scheduling techniques that have a low complexity and yet produce good quality schedules. The Time-Constrained Scheduling (TCS) problem minimizes the number of functional units required to schedule a particular Data Flow Graph (DFG) within a specified number of time steps. Over the past few years a number of techniques have been proposed to solve the TCS problem. Heuristic list scheduling algorithms have been widely used for their low-complexity and good performance. The complexity of a dynamic-list scheduling algorithm, such as the Force Directed Scheduling (FDS), is Θ(T*N2), where T is the time constraint and N is the number of operations. Static-list scheduling algorithms are the least complex among the known class of scheduling techniques with a linear time complexity of Θ(T*N). Typically, static-list scheduling algorithms, in order to maintain low-complexity, do not perform any look-ahead like that of FDS. The drawback is that, static-list scheduling algorithms may not generate high-quality schedules. However, the proposed static-list algorithm presented here incorporates a novel topological clustering technique which acts as the look-ahead mechanism without any computational overhead
Keywords :
computational complexity; data flow graphs; high level synthesis; scheduling; CAD; DFG; HLS; data flow graph; design space exploration; high-level synthesis; high-quality schedules; linear time complexity; look-ahead mechanism; low complexity; schedule quality improvement; static-list time-constrained scheduling; topological clustering technique; Clustering algorithms; Cost function; High level synthesis; Optimal scheduling; Parallel processing; Processor scheduling; Rubber; Scheduling algorithm; Space exploration; Time factors;
Conference_Titel :
Design, Automation and Test in Europe Conference and Exhibition 2000. Proceedings
Conference_Location :
Paris
Print_ISBN :
0-7695-0537-6
DOI :
10.1109/DATE.2000.840882