An efficient hardware-based XML message processing architecture

In the distributed computing environment, XML becomes the main choice as the way to transfer and store data in Web Services and distributed systems. With the development of the Web Services technique, there is a higher demand for an efficient XML message processing in some real-time systems. The XML messages are always parsed by software. Although many software-based XML processing techniques have been studied to improve the processing efficiency, this cannot help much. Hardware-based methods can be another efficient choice of boosting XML message processing. In this paper, we present a novel hardware-based XML message processing technique and design a binary token descriptor data structure to describe the document´s structure and information. By utilizing the processing technique we are able to parse the XML into a set of binary token descriptor. The architecture is designed and implemented on a FPGA. Our experimental results show that the processing rate is more efficient than the traditional software processing.