A test-vehicle for characterization of submicron transistors and interconnects

Author

Bendhia, Sonia Delmas ; Caignet, Fabrice ; Sicard, Etienne

Author_Institution

Inst. Nat. des Sci. Appliquees, Toulouse, France

fYear

1998

fDate

2-4 Mar 1998

Firstpage

69

Lastpage

74

Abstract

A specific integrated circuit has been designed and sent to fabrication as a demonstrator for characterization of submicron MOSFET devices and multilayer interconnects. The circuit implementation consists in two main parts, one dedicated to MOS model extraction, an other dealing with interconnect characterization from a dynamic and static point of view

Keywords

CMOS integrated circuits; MOSFET; SPICE; accumulation layers; circuit simulation; contact resistance; integrated circuit interconnections; integrated circuit modelling; semiconductor device models; ALFA chip MOSFET; MOS model extraction; N-well gated resistor; SPICE; accumulation layers; circuit implementation; circuit simulation; contact resistance; crosstalk effect; demonstrator IC; electrothermal structure; interconnect characterization; multilayer interconnects; parasitic parameters; propagation time; sampling sensors; submicron MOSFET devices; submicron transistors; Circuit simulation; Contact resistance; Current measurement; Electrical resistance measurement; Fabrication; Integrated circuit interconnections; MOS devices; MOSFET circuits; Temperature distribution; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Devices, Circuits and Systems, 1998. Proceedings of the 1998 Second IEEE International Caracas Conference on

Conference_Location

Isla de Margarita

Print_ISBN

0-7803-4434-0

Type

conf

DOI

10.1109/ICCDCS.1998.705808

Filename

705808