Title :
Improving the error detection ability of concurrent checkers by observation point insertion in the circuit under check
Author :
Vardanian, Valery A. ; Mirzoyan, Liana B.
Author_Institution :
STaR Lab., Inst. of Inf. & Autom. Problems, Yerevan, Armenia
Abstract :
Summary form only given. A heuristic design-for-checkability method based on observation point insertion in the Circuit Under Check (CUC) is proposed to increase the error detection ability of Concurrent Checkers (CC). In particular at least 99% of error detection is obtained for parity checkers and almost all ISCAS´85 benchmark circuits by inserting 2-5 groups of observation points compacted by parity trees
Keywords :
error detection; integrated circuit testing; logic testing; concurrent checkers; error detection ability; heuristic design-for-checkability method; observation point insertion; parity checkers; parity trees; Automation; Benchmark testing; Built-in self-test; Circuit testing; Compaction; Error analysis; Hardware; Informatics; Rails; Very large scale integration;
Conference_Titel :
Design, Automation and Test in Europe Conference and Exhibition 2000. Proceedings
Conference_Location :
Paris
Print_ISBN :
0-7695-0537-6
DOI :
10.1109/DATE.2000.840895
