DocumentCode
1982657
Title
Automated design of reliable checkers for control units using unidirectional error detecting codes
Author
Perelman, S. ; Levin, I. ; Ostrovsky, V.
Author_Institution
Tel Aviv Univ., Ramat-Aviv, Israel
fYear
2004
fDate
6-7 Sept. 2004
Firstpage
122
Lastpage
125
Abstract
This paper presents a CAD tool which incorporates several approaches to the design of reliable checkers for control units (devices which control the operation of other devices). Part of the approaches are traditional, part original. The main contribution of this paper is the automation of the design of checkers for lookup-table (LUT) based FPGA architecture, with aspiration to minimum hardware.
Keywords
CAD; error detection codes; field programmable gate arrays; logic testing; microcontrollers; table lookup; CAD tool; LUT based FPGA architecture; automated design; control units; lookup-table; minimum hardware; reliable checkers; unidirectional error detecting codes; Automatic control; Built-in self-test; Circuit faults; Design automation; Error correction codes; Field programmable gate arrays; Hardware; Microcontrollers; Postal services; Turning;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical and Electronics Engineers in Israel, 2004. Proceedings. 2004 23rd IEEE Convention of
Print_ISBN
0-7803-8427-X
Type
conf
DOI
10.1109/EEEI.2004.1361104
Filename
1361104
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