A VLSI-friendly ART1 neural algorithm and its CMOS analog current-mode implementation

We describe a modification to the original ART1 algorithm that is conceptually similar, can be implemented in hardware with less sophisticated components, and presents the same computational capabilities. We present a prototype chip for this modified ART1 algorithm fabricated in a standard low cost 1.5 μm double-metal single-poly CMOS process. It has a die area of 1 cm² and is mounted in a 120-pin PGA package. The chip implements an ART1 network with 100 F1 nodes and 18 F2 nodes. It can therefore cluster 100 binary pixels input patterns into up to 18 different categories. Modular expandability of the system is possible by assembling an N×M array of chips without any extra interfacing circuitry, resulting in an F1 layer with 100×N nodes, and an F2 layer with 18×M nodes. Pattern classification is performed in less than 1 μs, which means an equivalent computing power of 1.8×10⁹ connections per second